1. Field of the Invention
This invention relates generally to a method of manufacturing semiconductor devices and more specifically, this invention relates to a method of manufacturing semiconductor devices in which a layer of TiN formed on a surface of metal structures is removed after metal etch.
2. Discussion of the Related Art
In many of the current semiconductor manufacturing processes, the pad etch process consists of etching a layer of interlayer dielectric (ILD) and stopping on a layer of TiN on top of underlying metal structures. The layer of TiN is then etched completely down to the surface of the underlying metal structures. As is known in the semiconductor manufacturing art, pad etch is notoriously slow because of the substantial thickness of the final dielectric film and because of the requirement to completely remove the layer of TiN. The trend in the semiconductor manufacturing art is to make the layer of TiN sufficiently thick in order to prevent developer attack of the aluminum under TiN film, see the paper by E. G. Colgan, et al., “Formation Mechanism of Ring Defects during Metal RIE,” 1994 VMIC Conference, Jun. 7-8, 1994, page 284-286. Because it is necessary to completely remove the layer of TiN during pad etch so it will not interfere with the gold wire bonding process, the increased thickness of the layer of TiN increases the time required for pad etch.
FIGS. 1A-1I show a prior art method of manufacturing a semiconductor device in which the layer of TiN formed on metal structures are etched during the pad etch process.
FIG. 1A shows a partially completed semiconductor device 100. The partially completed semiconductor device 100 includes a layer of material 102 that is typically a layer of an interlayer dielectric (ILD) formed from a material such as silicon dioxide. The layer 102 of interlayer dielectric is formed under the final metal layer 104. The layer 104 is a layer of metal that will be etched to form conductive interconnects from one portion of the semiconductor device 100 that will form pads that will be connected to external structures during the gold wire bonding process. The layer 104 is typically formed from aluminum. A layer 106 of TiN is formed on the surface of the layer 104. The layer 106 of TIN serves as both a barrier layer and as an anti-reflective coating. A layer 108 of photoresist is formed on the surface of the layer 106 of TiN.
FIG. 1B shows the partially completed semiconductor device 100 as shown in FIG. 1A with the layer of photoresist 108 patterned and developed forming holes 110 and 112 in the layer 108 of photoresist that expose portions of the layer 106 of TiN.
FIG. 1C shows the partially completed semiconductor device 100 as shown in FIG. 1B after an etch process to etch the exposed portions of the layer 106 of TiN and exposing portions of the metal layer 104.
FIG. 1D shows the partially completed semiconductor device 100 as shown in FIG. 1C after an etch process to etch the exposed portions of the metal layer 104 down to the surface of the layer 102 of interlayer dielectric.
FIG. 1E shows the partially completed semiconductor device 100 as shown in FIG. 1D with the layer of photoresist 108 removed.
FIG. 1F shows the partially completed semiconductor device 100 as shown in FIG. 1E with a blanket layer 114 of interlayer dielectric formed on the surface of the semiconductor device 100 and filling the holes 110 and 112.
FIG. 1G shows the partially completed semiconductor device 100 as shown in FIG. 1F after a layer 116 of photoresist is formed on the surface of the layer 114 of interlayer dielectric. The layer 116 of photoresist is patterned and developed to form holes 118, 120, and 122 that expose portions of the layer 114 of interlayer dielectric.
FIG. 1H shows the partially completed semiconductor device 100 as shown in FIG. 1G after an etch process to etch exposed portions of the layer 114 of interlayer dielectric exposing portions of the layer 106 of TiN.
FIG. 1I shows the partially completed semiconductor device 100 as shown in FIG. 1H after an etch process to etch the exposed portions of the layer 106 of TiN.
The step of completely etching the layer 106 of TiN during the pad etch process causes a slow down in the throughput of the semiconductor device during the manufacturing process.
Therefore, what is needed is a manufacturing process that does not require the step of etching the TiN layer during pad etch.